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Features
* High Performance, Low Power AVR(R)32 UC 32-Bit Microcontroller
- Compact Single-cycle RISC Instruction Set Including DSP Instruction Set - Read-Modify-Write Instructions and Atomic Bit Manipulation - Performing 1.38 DMIPS / MHz Up to 75 DMIPS Running at 60 MHz from Flash Up to 45 DMIPS Running at 33 MHz from Fash - Memory Protection Unit Multi-hierarchy Bus System - High-Performance Data Transfers on Separate Buses for IIncreased Performance - 7 Peripheral DMA Channels Improves Speed for Peripheral Communication Internal High-Speed Flash - 256K Bytes, 128K Bytes, 64K Bytes Versions - Single Cycle Access up to 30 MHz - Prefetch Buffer Optimizing Instruction Execution at Maximum Speed - 4ms Page Programming Time and 8ms Full-Chip Erase Time - 100,000 Write Cycles, 15-year Data Retention Capability - Flash Security Locks and User Defined Configuration Area Internal High-Speed SRAM, Single-Cycle Access at Full Speed - 32K Bytes (256KB and 128KB Flash), 16K Bytes (64KB Flash) Interrupt Controller - Autovectored Low Latency Interrupt Service with Programmable Priority System Functions - Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator - Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL) allowing Independant CPU Frequency from USB Frequency - Watchdog Timer, Real-Time Clock Timer Universal Serial Bus (USB) - Device 2.0 Full/Low Speed and On-The-Go (OTG) - Flexible End-Point Configuration and Management with Dedicated DMA Channels - On-chip Transceivers Including Pull-Ups - USB Wake Up from Sleep Functionality One Three-Channel 16-bit Timer/Counter (TC) - Three External Clock Inputs, PWM, Capture and Various Counting Capabilities One 7-Channel 16-bit Pulse Width Modulation Controller (PWM) Three Universal Synchronous/Asynchronous Receiver/Transmitters (USART) - Independant Baudrate Generator, Support for SPI, IrDA and ISO7816 interfaces - Support for Hardware Handshaking, RS485 Interfaces and Modem Line One Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals One Synchronous Serial Protocol Controller - Supports I2S and Generic Frame-Based Protocols One Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible One 8-channel 10-bit Analog-To-Digital Converter On-Chip Debug System (JTAG interface) - Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace 64-pin TQFP/QFN (44 GPIO pins), 48-pin TQFP/QFN (28 GPIO pins) 5V Input Tolerant I/Os, including 4 high-drive pins. Single 3.3V Power Supply or Dual 1.8V-3.3V Power Supply
*
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AVR(R)32 32-Bit Microcontroller AT32UC3B0256 AT32UC3B0128 AT32UC3B064 AT32UC3B1256 AT32UC3B1128 AT32UC3B164 Preliminary Summary
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1. Description
The AT32UC3B is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 60 MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems. Higher computation capability is achieved using a rich set of DSP instructions. The AT32UC3B incorporates on-chip Flash and SRAM memories for secure and fast access. The Peripheral Direct Memory Access controller enables data transfers between peripherals and memories without processor involvement. PDC drastically reduces processing overhead when transferring continuous and large data streams between modules within the MCU. The Power Manager improves design flexibility and security: the on-chip Brown-Out Detector monitors the power supply, the CPU runs from the on-chip RC oscillator or from one of external oscillator sources, a Real-Time Clock and its associated timer keeps track of the time. The Timer/Counter includes three identical 16-bit timer/counter channels. Each channel can be independently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. The PWM modules provides seven independent channels with many configuration options including polarity, edge alignment and waveform non overlap control. One PWM channel can trigger ADC conversions for more accurate close loop control implementations. The AT32UC3B also features many communication interfaces for communication intensive applications. In addition to standard serial interfaces like UART, SPI or TWI, other interfaces like flexible Synchronous Serial Controller and USB are available. The Synchronous Serial Controller provides easy access to serial communication protocols and audio standards like I2S, UART or SPI. The Full-Speed USB 2.0 Device interface supports several USB Classes at the same time thanks to the rich End-Point configuration. The On-The-GO (OTG) Host interface allows device like a USB Flash disk or a USB printer to be directly connected to the processor. AT32UC3B integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control. The Nanotrace interface enables trace feature for JTAG-based debuggers.
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2. Configuration Summary
The table below lists all AT32UC3B memory and package configurations:
Device AT32UC3B0256 AT32UC3B0128 AT32UC3B064 AT32UC3B1256 AT32UC3B1128 AT32UC3B164
Flash 256 Kbytes 128 Kbytes 64 Kbytes 256 Kbytes 128 Kbytes 64 Kbytes
SRAM 32 Kbytes 32 Kbytes 16 Kbytes 32 Kbytes 32 Kbytes 16 Kbytes
USART 3 3 3 2 2 2
SSC 1 1 1 0 0 0
ADC 8 8 8 6 6 6
OSC 2 2 2 1 1 1
USB Configuration Mini-Host + Device Mini-Host + Device Mini-Host + Device Device Device Device
Package 64 lead TQFP/QFN 64 lead TQFP/QFN 64 lead TQFP/QFN 48 lead TQFP/QFN 48 lead TQFP/QFN 48 lead TQFP/QFN
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3. Blockdiagram
Figure 3-1.
TCK MEMORY INTERFACE TDO TDI TMS
Block diagram
JTAG INTERFACE
MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N LOCAL BUS INTERFACE
FAST GPIO
NEXUS CLASS 2+ OCD
UC CPU
MEMORY PROTECTION UNIT
INSTR INTERFACE
DATA INTERFACE
32 KB SRAM
USB INTERFACE DMA S M S
FLASH CONTROLLER
VBUS D+ DID VBOF
M
M
M
S
HIGH SPEED BUS MATRIX
S
256 KB FLASH
S
CONFIGURATION REGISTERS BUS HSB
M
PB
HSB-PB BRIDGE B GENERAL PURPOSE IOs
HS B
HSB-PB BRIDGE A
PB
PERIPHERAL DMA CONTROLLER
INTERRUPT CONTROLLER USART1
RXD TXD CLK RTS, CTS DSR, DTR, DCD, RI RXD TXD CLK RTS, CTS SCK NPCS[3..0] PDC
PA PB
EXTINT[7..0] KPS[7..0] NMI_N
EXTERNAL INTERRUPT CONTROLLER
REAL TIME COUNTER
USART0 USART2
PDC
WATCHDOG TIMER 115 kHz RCOSC
XIN32 XOUT32 XIN0 XOUT0 XIN1 XOUT1
POWER MANAGER CLOCK GENERATOR CLOCK CONTROLLER SLEEP CONTROLLER RESET CONTROLLER
SYNCHRONOUS SERIAL CONTROLLER
TX_CLOCK, TX_FRAME_SYNC TX_DATA RX_CLOCK, RX_FRAME_SYNC RX_DATA
GENERAL PURPOSE IOs
SERIAL PERIPHERAL INTERFACE
PDC
MISO, MOSI
32 KHz OSC OSC0 OSC1 PLL0 PLL1
GCLK[3..0] RESET_N
PDC
PA PB
TWO-WIRE INTERFACE
PDC
SCL SDA
PULSE WIDTH MODULATION CONTROLLER ANALOG TO DIGITAL CONVERTER
PDC
PWM[6..0]
PDC
AD[7..0] ADVREF
A[2..0] B[2..0] CLK[2..0]
TIMER/COUNTER
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3.1
3.1.1
Processor and architecture
AVR32UC CPU * 32-bit load/store AVR32A RISC architecture.
15 general-purpose 32-bit registers. 32-bit Stack Pointer, Program Counter and Link Register reside in register file. Fully orthogonal instruction set. Privileged and unprivileged modes enabling efficient and secure Operating Systems. Innovative instruction set together with variable instruction length ensuring industry leading code density. - DSP extention with saturating arithmetic, and a wide variety of multiply instructions. * 3 stage pipeline allows one instruction per clock cycle for most instructions. - Byte, half-word, word and double word memory access. - Multiple interrupt priority levels. * MPU allows for operating systems with memory protection. - - - - -
3.1.2
Debug and Test system * IEEE1149.1 compliant JTAG and boundary scan * Direct memory access and programming capabilities through JTAG interface * Extensive On-Chip Debug features in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+
- Low-cost NanoTrace supported.
3.1.3
* Auxiliary port for high-speed trace information * Hardware support for 6 Program and 2 data breakpoints * Unlimited number of software breakpoints supported * Advanced Program, Data, Ownership, and Watchpoint trace supported Peripheral DMA Controller (PDCA) * Transfers from/to peripheral to/from any memory space without intervention of the processor. * Next Pointer Support, forbids strong real-time constraints on buffer management. * 7 channels that can be dynamically attributed to
- - - - - all USARTs the Serial Synchronous Controller the Serial Peripheral Interface the ADC the TWI Interface
3.1.4
Bus system * High Speed Bus (HSB) matrixs
- Handles Requests from Masters: the CPU (instruction and Data Fetch), PDCA, USBB, CPU SAB, Slaves: the internal Flash, internal SRAM, Peripheral Bus A, Peripheral Bus B, USBB. - Round-Robin Arbitration (three modes supported: no default master, last accessed default
master, fixed default master)
- - - - Burst Breaking with Slot Cycle Limit One Address Decoder Provided per Master Peripheral Bus A able to run on at divided bus speeds compared to the High Speed Bus All modules connected to the same bus use the same clock, but the clock to each module can be individually shut off by the Power Manager.
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4. Package and Pinout
The device pins are multiplexed with peripheral functions as described in "Peripheral Multiplexing on I/O lines" on page 24. Figure 4-1. QFP64 Pinout
47 48
32 31
64 1 15
16
Table 4-1.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
QFP64 Package Pinout
GND TCK TDI TDO TMS PB00 PB01 VDDCORE PA03 PA04 PA05 PA06 PA07 PA08 PA30 PA31 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND ADVREF VDDANA VDDOUT VDDIN VDDCORE GND PB02 PB03 PB04 PB05 PA09 PA10 PA11 PA12 VDDIO 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PA13 PA14 PA15 PA16 PA17 PB06 PA18 PA19 PA28 PA29 PB07 PA20 PA21 PA22 PA23 VDDIO 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 GND DP DM VBUS VDDPLL PB08 PB09 VDDCORE PB10 PB11 PA24 PA25 PA26 PA27 RESET_N VDDIO
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Figure 4-2. QFP48 Pinout
36 37
25 24
48 1 12
13
Table 4-2.
1 2 3 4 5 6 7 8 9 10 11 12
QFP48 Package Pinout
GND TCK TDI TDO TMS VDDCORE PA03 PA04 PA05 PA06 PA07 PA08 13 14 15 16 17 18 19 20 21 22 23 24 GND ADVREF VDDANA VDDOUT VDDIN VDDCORE GND PA09 PA10 PA11 PA12 VDDIO 25 26 27 28 29 30 31 32 33 34 35 36 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 VDDIO 37 38 39 40 41 42 43 44 45 46 47 48 GND DP DM VBUS VDDPLL VDDCORE PA24 PA25 PA26 PA27 RESET_N VDDIO
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5. Signals Description
The following table gives details on the signal name classified by peripheral The signals are multiplexed with GPIO pins as described in "Peripheral Multiplexing on I/O lines" on page 24.
Table 5-1.
Signal Name
Signal Description List
Function Power Type Active Level Comments
VDDPLL
PLL Power Supply
Power Input Power Input Power Input Power Input Power Input Power Output Ground Ground Clocks, Oscillators, and PLL's
1.65V to 1.95 V
VDDCORE
Core Power Supply
1.65V to 1.95 V
VDDIO
I/O Power Supply
3.0V to 3.6V
VDDANA
Analog Power Supply
3.0V to 3.6V
VDDIN
Voltage Regulator Input Supply
3.0V to 3.6V
VDDOUT GNDANA GND
Voltage Regulator Output Analog Ground Ground
1.65V to 1.95 V
XIN0, XIN1, XIN32 XOUT0, XOUT1, XOUT32
Crystal 0, 1, 32 Input Crystal 0, 1, 32 Output JTAG
Analog Analog
TCK TDI TDO TMS
Test Clock Test Data In Test Data Out Test Mode Select
Input Input Output Input Auxiliary Port - AUX
MCKO MDO0 - MDO5
Trace Data Output Clock Trace Data Output
Output Output
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Table 5-1.
Signal Name MSEO0 - MSEO1 EVTI_N EVTO_N
Signal Description List
Function Trace Frame Control Event In Event Out Type Output Output Output Power Manager - PM Low Low Active Level Comments
GCLK0 - GCLK2 RESET_N
Generic Clock Pins Reset Pin
Output Input External Interrupt Module - EIM Low
EXTINT0 - EXTINT7 KPS0 - KPS7 NMI_N
External Interrupt Pins Keypad Scan Pins Non-Maskable Interrupt Pin
Input Output Input Low
General Purpose I/O pin- GPIOA, GPIOB PA0 - PA31 PB0 - PB11 Parallel I/O Controller GPIOA Parallel I/O Controller GPIOB I/O I/O
Serial Peripheral Interface - SPI0 MISO MOSI NPCS0 - NPCS3 SCK Master In Slave Out Master Out Slave In SPI Peripheral Chip Select Clock I/O I/O I/O Output Synchronous Serial Controller - SSC RX_CLOCK RX_DATA RX_FRAME_SYNC TX_CLOCK TX_DATA TX_FRAME_SYNC SSC Receive Clock SSC Receive Data SSC Receive Frame Sync SSC Transmit Clock SSC Transmit Data SSC Transmit Frame Sync I/O Input I/O I/O Output I/O Timer/Counter - TIMER A0 A1 Channel 0 Line A Channel 1 Line A I/O I/O Low
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Table 5-1.
Signal Name A2 B0 B1 B2 CLK0 CLK1 CLK2
Signal Description List
Function Channel 2 Line A Channel 0 Line B Channel 1 Line B Channel 2 Line B Channel 0 External Clock Input Channel 1 External Clock Input Channel 2 External Clock Input Type I/O I/O I/O I/O Input Input Input Active Level Comments
Two-wire Interface - TWI SCL SDA Serial Clock Serial Data I/O I/O
Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2 CLK CTS DCD DSR DTR RI RTS RXD TXD Clock Clear To Send Data Carrier Detect Data Set Ready Data Terminal Ready Ring Indicator Request To Send Receive Data Transmit Data Output Input Output Analog to Digital Converter - ADC AD0 - AD7 Analog input pins Analog input Analog input 2.6 to 3.6V I/O Input Only USART1 Only USART1 Only USART1 Only USART1
ADVREF
Analog positive reference voltage input
Pulse Width Modulator - PWM PWM0 - PWM6 PWM Output Pins Output Universal Serial Bus Device - USB DDM USB Device Port Data Analog
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Table 5-1.
Signal Name DDP VBUS USBID USB_VBOF
Signal Description List
Function USB Device Port Data + USB VBUS Monitor and OTG Negociation ID Pin of the USB Bus USB VBUS On/off: bus power control port Type Analog Analog Input Input output Active Level Comments
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6. Power Considerations
6.1 Power Supplies
The AT32UC3B has several types of power supply pins: * * * * *
VDDIO: Powers I/O lines. Voltage is 3.3V nominal. VDDANA: Powers the ADC Voltage is 3.3V nominal. VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V nominal. VDDCORE: Powers the core, memories, and peripherals. Voltage is 1.8V nominal. VDDPLL: Powers the PLL. Voltage is 1.8V nominal.
The ground pins GND are common to VDDCORE, VDDIO and VDDPLL. The ground pin for VDDANA is GNDANA. Refer to "Electrical Characteristics" on page 30 for power consumption on the various supply pins. The main requirement for power supplies connection is to respect a star topology for all electrical connection.
Dual Power Supply Single Power Supply
3.3V
VDDAN A VDDI O
3.3V
VDDAN A VDDI O
ADVREF
ADVREF
VDDI N VDDOU T VDDCOR E
VDDI N
1.8V Regulator
1.8V Regulator
VDDOU T 1.8 V VDDCOR E
VDDPL L
VDDPL L
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6.2
6.2.1
Voltage Regulator
Single Power Supply The AT32UC3B embeds a voltage regulator that converts from 3.3V to 1.8V. The regulator takes its input voltage from VDDIN, and supplies the output voltage on VDDOUT that should be externally connected to the 1.8V domains. Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. Two input decoupling capacitors must be placed close to the chip. Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel between VDDOUT and GND as close to the chip as possible
3.3V CIN2 CIN1
VDDIN
1.8V Regulator
VDDOUT
1.8V COUT2 COUT1
Refer to Section 11.3 on page 32 for decoupling capacitors values and regulator characteristics.
6.2.2
Dual Power Supply In case of dual power supply, VDDIN and VDDOUT should be connected to ground to prevent from leakage current.
VDDIN
VDDOUT
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6.3 Analog-to-Digital Converter (A.D.C) reference.
The ADC reference (ADVREF) must be provided from an external source. Two decoupling capacitors must be used to insure proper decoupling.
3.3V C
VREF2
ADVREF C
VREF1
Refer to Section 11.4 on page 32 for decoupling capacitors values and electrical characteristics.
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7. I/O Line Considerations
7.1 JTAG pins
TMS and TDI pins have pull-up resistors. TDO pin is an output, driven at up to VDDIO, and has no pull-up resistor. These 3 pins can be used as GPIO-pins. At reset state, these pins are in GPIO mode. TCK pin cannot be used as GPIO pin. JTAG interface is enabled when TCK pin is tied low. This pins must be pulled-up externally on application board.
7.2
RESET_N pin
The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product.
7.3
TWI pins
When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike-filtering. When used as GPIO-pins or used for other peripherals, the pins have the same characteristics as PIO pins.
7.4
GPIO pins
All the I/O lines integrate a pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the GPIO Controllers. After reset, I/O lines default as inputs with pull-up resistors disabled, except when indicated otherwise in the column "Reset State" of the GPIO Controller multiplexing tables.
7.5
High drive pins
The four pins PA20, PA21, PA22, PA23 have high drive output capabilities. Refer to Figure 11. on page 30 for electrical characteristics.
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8. Memories
8.1 Embedded Memories
* Internal High-Speed Flash
- 256 KBytes (AT32UC3B0256, AT32UC3B1256) - 128 KBytes (AT32UC3B0128, AT32UC3B1128) - 64 KBytes (AT32UC3B064, AT32UC3B164) - 0 Wait State Access at up to 30 MHz in Worst Case Conditions - 1 Wait State Access at up to 60 MHz in Worst Case Conditions - Pipelined Flash Architecture, allowing burst reads from sequential Flash locations, hiding penalty of 1 wait state access - Pipelined Flash Architecture typically reduces the cycle penalty of 1 wait state operation to only 8% compared to 0 wait state operation - 100 000 Write Cycles, 15-year Data Retention Capability - 4 ms Page Programming Time, 8 ms Chip Erase Time - Sector Lock Capabilities, Bootloader Protection, Security Bit - 32 Fuses, Erased During Chip Erase - User Page For Data To Be Preserved During Chip Erase * Internal High-Speed SRAM, Single-cycle access at full speed - 32KBytes (AT32UC3B0256, AT32UC3B0128, AT32UC3B1256 and AT32UC3B1128) - 16KBytes (AT32UC3B064 and AT32UC3B164)
8.2
Physical Memory Map
The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AVR32 UC CPU uses unsegmented translation, as described in the AVR32 Architecture Manual. The 32-bit physical address space is mapped as follows:
Table 8-1.
Device
AT32UC3B Physical Memory Map
Start Address 0x0000_0000 0x8000_0000 0xD000_0000 0xFFFE_0000 0xFFFF_0000 Size
AT32UC3B0256 AT32UC3B1256 AT32UC3B0128 AT32UC3B1128 AT32UC3B064 AT32UC3B164
Embedded SRAM Embedded Flash USB Configuration HSB-PB Bridge A HSB-PB Bridge B
32 Kbytes 256 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes
32 Kbytes 256 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes
32 Kbytes 128 Kbytes 64 Kbytes 64 Kbytes 64 kBytes
32 Kbytes 128 Kbytes 64 Kbytes 64 Kbytes 64 kBytes
16 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes
16 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes
Table 8-2.
Flash Memory Parameters
Flash Size (FLASH_PW) 256 Kbytes 256 Kbytes 128 Kbytes Number of pages (FLASH_P) 512 512 256 Page size (FLASH_W) 128 words 128 words 128 words
Part Number AT32UC3B0256 AT32UC3B1256 AT32UC3B0128
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Table 8-2. Flash Memory Parameters
128 Kbytes 64 Kbytes 64 Kbytes 256 128 128 128 words 128 words 128 words AT32UC3B1128 AT32UC3B064 AT32UC3B164
8.3
Bus Matrix Connections
Accesses to unused areas returns an error result to the master requesting such an access. The bus matrix has the several masters and slaves. Each master has its own bus and its own decoder, thus allowing a different memory mapping per master. The master number in the table below can be used to index the HMATRIX control registers. For example, HMATRIX MCFG0 register is associated with the CPU Data master interface. Table 8-3.
Master 0 Master 1 Master 2 Master 3 Master 4
High Speed Bus masters
CPU Data CPU Instruction CPU SAB PDCA USBB DMA
Each slave has its own arbiter, thus allowing a different arbitration per slave. The slave number in the table below can be used to index the HMATRIX control registers. For example, SCFG3 is associated with the Internal SRAM Slave Interface. Table 8-4.
Slave 0 Slave 1 Slave 2 Slave 3 Slave 4
High Speed Bus slaves
Internal Flash HSB-PB Bridge 0 HSB-PB Bridge 1 Internal SRAM USBB DPRAM
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Figure 8-1. HMatrix Master / Slave Connections
HMATRIX SLAVES USBB DPRAM 4 Internal SRAM 3
Internal Flash
HSB-PB Bridge 0 1
0
CPU Data
0
HMATRIX MASTERS
CPU Instruction
1
CPU SAB
2
PDCA
3
USBB DMA
4
HSB-PB Bridge 1 2
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9. Peripherals
9.1 Peripheral Address Map
Peripheral Address Mapping
Address
0xFFFE0000
Table 9-1.
Peripheral Name USBB USB 2.0 OTG - USBB
Bus
PBB
0xFFFE1000
HMATRIX
0xFFFE1400
HMATRIX Configuration Interface - HMATRIX
PBB
FLASHC
0xFFFF0000
Flash controller - FLASHC
PBB
PDCA
0xFFFF0800
Peripheral Direct Memory Access - PDCA
PBA
INTC
0xFFFF0C00
Interrupt controller - INTC
PBA
PM
0xFFFF0D00
Power Manager - PM
PBA
RTC
0xFFFF0D30
Real Time Counter - RTC
PBA
WDT
0xFFFF0D80
Watchdog Timer - WDT
PBA
EIC
0xFFFF1000
External Interrupt Controller - EIC
PBA
GPIO
0xFFFF1400
General Purpose Input/Output - GPIO Universal Synchronous Asynchronous Receiver Transmitter - USART0 Universal Synchronous Asynchronous Receiver Transmitter - USART1 Universal Synchronous Asynchronous Receiver Transmitter - USART2 Serial Peripheral Interface - SPI
PBA
USART0
0xFFFF1800
PBA
USART1
0xFFFF1C00
PBA
USART2
0xFFFF2400
PBA
SPI
0xFFFF2C00
PBA
TWI
0xFFFF3000
Two-wire Interface - TWI
PBA
PWM
0xFFFF3400
Pulse Width Modulation Controller - PWM
PBA
SSC
Synchronous Serial Controller - SSC
PBA
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Table 9-1. Peripheral Address Mapping
0xFFFF3800
TC
0xFFFF3C00
Timer/Counter - TC
PBA
ADC
Analog to Digital Converter - ADC
PBA
9.2
CPU Local Bus Mapping
Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can therefore be reached both by accesses on the Peripheral Bus, and by accesses on the local bus. Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at CPU speed, one write or read operation can be performed per clock cycle to the local busmapped GPIO registers. The following GPIO registers are mapped on the local bus: Table 9-2.
Port A
Local bus mapped GPIO registers
Mode WRITE SET CLEAR TOGGLE Local Bus Address 0x4000_0040 0x4000_0044 0x4000_0048 0x4000_004C 0x4000_0050 0x4000_0054 0x4000_0058 0x4000_005C 0x4000_0060 0x4000_0140 0x4000_0144 0x4000_0148 0x4000_014C 0x4000_0150 0x4000_0154 0x4000_0158 0x4000_015C 0x4000_0160 Access Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only
Register Output Driver Enable Register (ODER)
Output Value Register (OVR)
WRITE SET CLEAR TOGGLE
Pin Value Register (PVR) B Output Driver Enable Register (ODER)
WRITE SET CLEAR TOGGLE
Output Value Register (OVR)
WRITE SET CLEAR TOGGLE
Pin Value Register (PVR)
-
9.3
Interrupt Request Signal Map
The various modules may output Interrupt request signals. These signals are routed to the Interrupt Controller (INTC), described in a later chapter. The Interrupt Controller supports up to 64
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groups of interrupt requests. Each group can have up to 32 interrupt request signals. All interrupt signals in the same group share the same autovector address and priority level. Refer to the documentation for the individual submodules for a description of the semantic of the different interrupt requests. The interrupt request signals are connected to the INTC as follows. Table 9-3.
Group 0
Interrupt Request Signal Map
Line 0 0 1 2 3 4 Module AVR32 UC CPU with optional MPU and optional OCD External Interrupt Controller External Interrupt Controller External Interrupt Controller External Interrupt Controller External Interrupt Controller External Interrupt Controller External Interrupt Controller External Interrupt Controller Real Time Counter Power Manager General Purpose Input/Output General Purpose Input/Output General Purpose Input/Output General Purpose Input/Output General Purpose Input/Output General Purpose Input/Output Peripheral Direct Memory Access Peripheral Direct Memory Access Peripheral Direct Memory Access Peripheral Direct Memory Access Peripheral Direct Memory Access Peripheral Direct Memory Access Peripheral Direct Memory Access Flash controller Universal Synchronous Asynchronous Receiver Transmitter Universal Synchronous Asynchronous Receiver Transmitter Universal Synchronous Asynchronous Receiver Transmitter Signal SYSBLOCK COMPARE EIC 0 EIC 1 EIC 2 EIC 3 EIC 4 EIC 5 EIC 6 EIC 7 RTC PM GPIO 0 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 PDCA 0 PDCA 1 PDCA 2 PDCA 3 PDCA 4 PDCA 5 PDCA 6 FLASHC USART0 USART1 USART2
1 5 6 7 8 9 0 1 2 2 3 4 5 0 1 2 3 3 4 5 6 4 5 6 7 0 0 0 0
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Table 9-3.
9 11 12 13
Interrupt Request Signal Map
0 0 0 0 0 Serial Peripheral Interface Two-wire Interface Pulse Width Modulation Controller Synchronous Serial Controller Timer/Counter Timer/Counter Timer/Counter Analog to Digital Converter USB 2.0 OTG SPI TWI PWM SSC TC0 TC1 TC2 ADC USBB
14
1 2
15 17
0 0
9.4
9.4.1
Clock Connections
Timer/Counters Each Timer/Counter channel can independently select an internal or external clock source for its counter: Table 9-4.
Source Internal
Timer/Counter clock connections
Name TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 Connection Slow Clock (Internal RC oscillator) PBA Clock / 2 PBA Clock / 8 PBA Clock / 32 PBA Clock / 128 See Section 9.8
External
XC0 XC1 XC2
9.4.2
USARTs Each USART can be connected to an internally divided clock: Table 9-5.
USART 0 1 2
USART clock connections
Source Internal Name CLK_DIV Connection PBA Clock / 8
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9.4.3 SPIs SPI can be connected to an internally divided clock: Table 9-6.
SPI 0
SPI clock connections
Source Internal Name CLK_DIV Connection PBA clock or PBA clock / 32
9.5
Nexus OCD AUX port connections
If the OCD trace system is enabled, the trace system will take control over a number of pins, irrespectively of the PIO configuration. Two different OCD trace pin mappings are possible, depending on the configuration of the OCD AXS register. For details, see the AVR32 UCTechnical Reference Manual. Table 9-7.
Pin EVTI_N MDO[5] MDO[4] MDO[3] MDO[2] MDO[1] MDO[0] EVTO_N MCKO MSEO[1] MSEO[0]
Nexus OCD AUX port connections
AXS=0 PB05 PB04 PB03 PB02 PB01 PB00 PA31 PA15 PA30 PB06 PB07 AXS=1 PA14 PA08 PA07 PA06 PA05 PA03 PA02 PA15 PA13 PA09 PA10
9.6
DMA handshake signals
The PDCA and the peripheral modules communicate through a set of handshake signals. The following table defines the valid settings for the Peripheral Identifier (PID) in the PDCA Peripheral Select Register (PSR).
Table 9-8.
PID Value 0 1 2 3 4
PDCA Handshake Signals
Peripheral module & direction ADC SSC - RX USART0 - RX USART1 - RX USART2 - RX
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Table 9-8.
PID Value 5 6 7 8 9 10 11 12
PDCA Handshake Signals
Peripheral module & direction TWI - RX SPI0 - RX SSC - TX USART0 - TX USART1 - TX USART2 - TX TWI - TX SPI0 - TX
9.7
High Drive Current GPIO
Ones of GPIOs can be used to drive twice current than other GPIO capability (see Electrical Characteristics chapter). The list of those GPIOs is shown in Table 9-9. Table 9-9.
GPIO Name GPIO/0/P21 GPIO/0/P22 GPIO/0/P23 GPIO/0/P24
High Drive Current GPIO
9.8
Peripheral Multiplexing on I/O lines
Each GPIO line can be assigned to one of 3 peripheral functions; A, B or C. The following table define how the I/O lines on the peripherals A, B and C are multiplexed by the GPIO.
Table 9-10.
QFP48 7 8 9 10 11 12 20 21 22 23 25
GPIO Controller Function Multiplexing
QFP64 9 10 11 12 13 14 28 29 30 31 33 PIN PA03 PA04 PA05 PA06 PA07 PA08 PA09 PA10 PA11 PA12 PA13 GPIO Pin GPIO 3 GPIO 4 GPIO 5 GPIO 6 GPIO 7 GPIO 8 GPIO 9 GPIO 10 GPIO 11 GPIO 12 GPIO 13 Function A ADC - AD[0] ADC - AD[1] EIC - EXTINT[0] EIC - EXTINT[1] PWM - PWM[0] PWM - PWM[1] TWI - SCL TWI - SDA USART0 - RTS USART0 - CTS NMI Function B PM - GCLK[0] PM - GCLK[1] ADC - AD[2] ADC - AD[3] ADC - AD[4] ADC - AD[5] SPI - NPCS[2] SPI - NPCS[3] TC - A2 TC - B2 PWM - PWM[2] Function C USBB - USB_ID USBB - USB_VBOF USART1 - DCD USART1 - DSR USART1 - DTR USART1 - RI USART1 - CTS USART1 - RTS PWM - PWM[0] PWM - PWM[1] USART0 - CLK
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Table 9-10.
26 27 28 29 30 31 32 33 34 35 43 44 45 46
GPIO Controller Function Multiplexing
34 35 36 37 39 40 44 45 46 47 59 60 61 62 41 42 15 16 6 7 24 25 26 27 38 43 54 55 57 58 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PB00 PB01 PB02 PB03 PB04 PB05 PB06 PB07 PB08 PB09 PB10 PB11 TDI TDO TMS GPIO 14 GPIO 15 GPIO 16 GPIO 17 GPIO 18 GPIO 19 GPIO 20 GPIO 21 GPIO 22 GPIO 23 GPIO 24 GPIO 25 GPIO 26 GPIO 27 GPIO 28 GPIO 29 GPIO 30 GPIO 31 GPIO 32 GPIO 33 GPIO 34 GPIO 35 GPIO 36 GPIO 37 GPIO 38 GPIO 39 GPIO 40 GPIO 41 GPIO 42 GPIO 43 GPIO 0 GPIO 1 GPIO 2 SPI - MOSI SPI - SCK SPI - NPCS[0] SPI - NPCS[1] USART0 - RXD USART0 - TXD USART1 - CLK PWM - PWM[2] PWM - PWM[6] USART1 - TXD USART1 - RXD SPI - MISO USBB - USB_ID USBB - USB_VBOF USART0 - CLK TC - CLK0 ADC - AD[6] ADC - AD[7] TC - A0 TC - B0 EIC - EXTINT[6] EIC - EXTINT[7] USART1 - CTS USART1 - RTS SSC - RX_CLOCK SSC - RX_DATA SSC RX_FRAME_SYNC SSC - TX_CLOCK SSC - TX_DATA SSC TX_FRAME_SYNC PWM - PWM[3] PWM - PWM[4] TC - CLK1 TC - CLK2 PWM - PWM[5] PWM - PWM[6] TC - CLK0 TC - A1 TC - B1 SPI - NPCS[1] SPI - NPCS[0] PWM - PWM[3] USART2 - TXD USART2 - RXD PWM - PWM[4] TC - CLK1 EIC - SCAN[0] EIC - SCAN[1] EIC - SCAN[2] EIC - SCAN[3] TC - A1 TC - B1 SPI - NPCS[3] SPI - NPCS[2] USART1 - DCD USART1 - DSR USART1 - DTR USART1 - RI TC - A2 TC - B2 USART2 - CTS USART2 - RTS USART1 - TXD USART1 - RXD TC - CLK2 PWM - PWM[5] EIC - SCAN[4] EIC - SCAN[5] EIC - SCAN[6] EIC - SCAN[7] USART0 - RXD USART0 - TXD SPI - SCK SPI - MISO SPI - MOSI USART2 - RXD USART2 - TXD ADC - TRIGGER EIC - EXTINT[3] EIC - EXTINT[4] EIC - EXTINT[5] TC - A0 TC - B0 SPI - MISO SPI - MOSI PM - GCLK[2] EIC - EXTINT[2] USART2 - CLK
3 4 5
3 4 5
9.9
Oscillator Pinout
The oscillators are not mapped to the normal A,B or C functions and their muxings are controlled by registers in the Power Manager (PM). Please refer to the power manager chapter for more information about this.
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Table 9-11.
Oscillator pinout
QFP64 pin 39 41 Pad PA18 PA28 PA11 PA19 PA29 PA12 Oscillator pin xin0 xin1 xin32 xout0 xout1 xout32
QFP48 pin 30
22 31
30 40 42
23
31
9.10
9.10.1
Peripheral overview
USB Controller * USB 2.0 Compliant, Full-/Low-Speed (FS/LS) and On-The-Go (OTG), 12 Mbit/s * 7 Pipes/Endpoints * 960 bytes of Embedded Dual-Port RAM (DPRAM) for Pipes/Endpoints * Up to 2 Memory Banks per Pipe/Endpoint (Not for Control Pipe/Endpoint) * Flexible Pipe/Endpoint Configuration and Management with Dedicated DMA Channels * On-Chip Transceivers Including Pull-Ups * System wake-up on USB line activity Serial Peripheral Interface * Supports communication with serial external devices
- Four chip selects with external decoder support allow communication with up to 15 peripherals - Serial memories, such as DataFlash and 3-wire EEPROMs - Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors - External co-processors * Master or slave serial peripheral bus interface - 8- to 16-bit programmable data length per chip select - Programmable phase and polarity per chip select - Programmable transfer delays between consecutive transfers and between clock and data per chip select - Programmable delay between consecutive transfers - Selectable mode fault detection * Very fast transfers supported - Transfers with baud rates up to Peripheral Bus A (PBA) max frequency - The chip select line may be left active to speed up transfers on the same device
9.10.2
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9.10.3 Two-wire Interface * * * * 9.10.4 USART * Programmable Baud Rate Generator * 5- to 9-bit full-duplex synchronous or asynchronous serial communications
- 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode - Parity generation and error detection - Framing error detection, overrun error detection - MSB- or LSB-first - Optional break generation and detection - By 8 or by-16 over-sampling receiver frequency - Hardware handshaking RTS-CTS - Receiver time-out and transmitter timeguard - Optional Multi-drop Mode with address generation and detection - Optional Manchester Encoding RS485 with driver control signal ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards - NACK handling, error counter with repetition and iteration limit IrDA modulation and demodulation - Communication at up to 115.2 Kbps Test Modes - Remote Loopback, Local Loopback, Automatic Echo SPI Mode - Master or Slave - Serial Clock Programmable Phase and Polarity - SPI Serial Clock (SCK) Frequency up to Internal Clock Frequency PBA/4 Supports Connection of Two Peripheral DMA Controller Channels (PDC) - Offers Buffer Transfer without Processor Intervention High speed up to 400kbit/s Compatibility with standard two-wire serial memory One, two or three bytes for slave address Sequential read/write operations
* * * * *
* 9.10.5
Serial Synchronous Controller * Provides serial synchronous communication links used in audio and telecom applications (with
CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.)
* Contains an independent receiver and transmitter and a common clock divider * Offers a configurable frame sync and data length * Receiver and transmitter can be programmed to start automatically or on detection of different
event on the frame sync signal
* Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 9.10.6 Timer Counter * Three 16-bit Timer Counter Channels * Wide range of functions including:
- - - - - Frequency Measurement Event Counting Interval Measurement Pulse Generation Delay Timing
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- Pulse Width Modulation - Up/down Capabilities * Each channel is user-configurable and contains: - Three external clock inputs - Five internal clock inputs - Two multi-purpose input/output signals * Two global registers that act on all three TC Channels
9.10.7
Pulse Width Modulation Controller * 7 channels, one 16-bit counter per channel * Common clock generator, providing Thirteen Different Clocks
- A Modulo n counter providing eleven clocks - Two independent Linear Dividers working on modulo n counter outputs * Independent channel programming - Independent Enable Disable Commands - Independent Clock - Independent Period and Duty Cycle, with Double Bufferization - Programmable selection of the output waveform polarity - Programmable center or left aligned output waveform
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10. Boot Sequence
This chapter summarizes the boot sequence of the AT32UC3B. The behaviour after power-up is controlled by the Power Manager. For specific details, refer to Section 13. "Power Manager (PM)" on page 45.
10.1
Starting of clocks
After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the power has stabilized throughout the device. Once the power has stabilized, the device will use the internal RC Oscillator as clock source. On system start-up, the PLLs are disabled. All clocks to all modules are running. No clocks have a divided frequency, all parts of the system recieves a clock with the same frequency as the internal RC Oscillator.
10.2
Fetching of initial instructions
After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset address, which is 0x8000_0000. This address points to the first address in the internal Flash. The code read from the internal Flash is free to configure the system to use for example the PLLs, to divide the frequency of the clock routed to some of the peripherals, and to gate the clocks to unused peripherals.
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11. Electrical Characteristics
11.1 Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Operating Temperature.................................... -40C to +85C Storage Temperature ..................................... -60C to +150C Voltage on GPIO Pins with respect to Ground ............................................. -0.3 to 5V Maximum Voltage on RESET_N Pin ................................ 3.3V Maximum Operating Voltage (VDDCORE, VDDPLL) ..... 1.95V Maximum Operating Voltage (VDDIO).............................. 3.6V Total DC Output Current on all I/O Pin for 48-pin package ....................................................... 200 mA for 64-pin package ....................................................... 265 mA
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11.2 DC Characteristics
The following characteristics are applicable to the operating temperature range: TA = -40C to 85C, unless otherwise specified and are certified for a junction temperature up to TJ = 100C.
Symbol VVDDCOR
E
Parameter DC Supply Core DC Supply PLL DC Supply Peripheral I/Os Analog reference voltage Input Low-level Voltage Input High-level Voltage Output Low-level Voltage Output High-level Voltage Input Leakage Current Input Capacitance Pull-up Resistance I/O Output Current
Condition
Min. 1.65 1.65 3.0 2.6 -0.3 2.0
Typ.
Max. 1.95 1.95 3.6 3.6 +0.8 VVDDIO+0. 3 0.4
Units V V V V V V V
VVDDPLL VVDDIO VREF VIL VIH VOL VOH ILEAK CIN RPULLUP IO
VVDDIO= VVDDIOM or VVDDIOP Pullup resistors disabled
VVDDIO-0.4 TBD TBD TBD 4 mA A A pF
On VVDDCORE = 1.8V, device in static mode ISC Static Current All inputs driven including JTAG; RESET_N=1 Low Power mode (stop, deep stop or static
TA =25C TA =85C TA =25C
6
25
A
ISCR
Static Current of internal regulator
10
A
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11.3
11.3.1
Symbol VVDDIN VVDDOUT IOUT
Regulator characteristics
Electrical characteristics
Parameter Supply voltage (input) Supply voltage (output) Maximum DC output current with VVDDIN = 3.3V Maximum DC output current with VVDDIN = 2.7V Condition Min. 2.7 1.81 Typ. 3.3 1.85 Max. 3.6 1.89 100 90 Units V V mA mA
11.3.2
Symbol CIN1 CIN2 COUT1 COUT2
Decoupling requirements
Parameter Input Regulator Capacitor 1 Input Regulator Capacitor 2 Output Regulator Capacitor 1 Output Regulator Capacitor 2 Condition Typ. 1 4.7 470 2.2 Techno. NPO X7R NPO X7R Units nF uF pF uF
11.4
11.4.1
Analog characteristics
Electrical characteristics
Parameter Analog voltage reference (input) Condition Min. 2.6 Typ. Max. 3.6 Units V
Symbol VADVREF
11.4.2
Symbol CVREF1 CVREF2
Decoupling requirements
Parameter Voltage reference Capacitor 1 Voltage reference Capacitor 2 Condition Typ. 10 1 Techno. Units nF uF
11.4.3
BOD Table 11-1. BODLEVEL Values
Typ. Units.
BODLEVEL Value
000000b 010111b 011111b 100111b 111111b
1.58 1.62 1.67 1.77 1.92
V V V V V
The values in Table 11-1 describes the values of the BODLEVEL in the flash General Purpose Fuse register.
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11.5 Power Consumption
The values in Table 11-2 and Table 11-3 on page 34 are measured values of power consumption with operating conditions as follows: *VDDIO = 3.3V *VDDCORE = VDDPLL = 1.8V *TA = 25C, TA = 85C *I/Os are inactive Figure 11-1. Measure schematic
VDDANA
VDDIO
Amp0
VDDIN
Internal Voltage Regulator
VDDOUT
Amp2
VDDCORE
VDDPLL
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These figures represent the power consumption measured on the power supplies. Table 11-2.
Mode
Power Consumption for Different Modes(1)
Conditions CPU running from flash. CPU clocked from PLL0 at f MHz Voltage regulator is on. XIN0 : external clock. (1) XIN1 stopped. XIN32 stopped PLL0 running All peripheral clocks activated. GPIOs on internal pull-up. JTAG unconnected with ext pull-up. Typ : Ta = 25 C CPU is in static mode GPIOs on internal pull-up. All peripheral clocks de-activated. DM and DP pins connected to ground. XIN0,Xin1 and XIN2 are stopped f = 12 MHz f = 24 MHz f = 36MHz f = 50 MHz Consumption Typ. 5.5 10 14.5 19.5 Unit mA mA mA mA
Active
f = 60 MHz
23.5
mA
on Amp0
15.5
uA
Static
on Amp1
6
uA
1. Core frequency is generated from XIN0 using the PLL so that 140 MHz < fpll0 < 160 MHz and 10 MHz < fxin0 < 12MHz.
Table 11-3.
Peripheral INTC GPIO PDCA USART USB ADC TWI PWM SPI SSC TC
Power Consumption by Peripheral in Active Mode
Consumption 20 27 27 35 30 18 14 26 11 35 26 A/MHz Unit
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11.6 Clock Characteristics
These parameters are given in the following conditions: * VDDCORE = 1.8V * Ambient Temperature = 25C 11.6.1 CPU/HSB Clock Characteristics Core Clock Waveform Parameters
Parameter CPU Clock Frequency CPU Clock Period 16.6 Conditions Min Max 60 Units MHz ns
Table 11-4.
Symbol 1/(tCPCPU) tCPCPU
11.6.2
PBA Clock Characteristics PBA Clock Waveform Parameters
Parameter PBA Clock Frequency PBA Clock Period 16.6 Conditions Min Max 60 Units MHz ns
Table 11-5.
Symbol 1/(tCPPBA) tCPPBA
11.6.3
PBB Clock Characteristics PBB Clock Waveform Parameters
Parameter PBB Clock Frequency PBB Clock Period 16.6 Conditions Min Max 60 Units MHz ns
Table 11-6.
Symbol 1/(tCPPBB) tCPPBB
11.6.4
XIN Clock Characteristics XIN Clock Electrical Characteristics
Parameter XIN Clock Frequency XIN Clock Period XIN Clock High Half-period XIN Clock Low Half-period XIN Input Capacitance XIN Pulldown Resistor
(1) (1)
Table 11-7.
Symbol 1/(tCPXIN) tCPXIN tCHXIN tCLXIN CIN RIN Note:
Conditions
Min 3 41.0 0.4 x tCPXIN 0.4 x tCPXIN 12
Max 24
Units MHz ns
0.6 x tCPXIN 0.6 x tCPXIN pF TBD k
1. These characteristics apply only when the Main Oscillator is in bypass mode.
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11.6.5 RESET_N Characteristics RESET_N Clock Waveform Parameters
Parameter RESET_N minimum pulse length Conditions Min 10 Max Units ns
Table 11-8.
Symbol tRESET
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11.7 Crystal Oscillator Characteristis
The following characteristics are applicable to the operating temperature range: TA = -40C to 85C and worst case of power supply, unless otherwise specified. 11.7.1 32 KHz Oscillator Characteristics 32 KHz Oscillator Characteristics
Parameter Crystal Oscillator Frequency Duty Cycle CL tST IOSC Equivalent Load Capacitance Startup Time CL = 6pF(1) CL = 12.5pF(1) Active mode Current Consumption Standby mode 1. CL is the equivalent load capacitance. 0.1 A 40 6 50 Conditions Min Typ Max 32 768 60 12.5 600 1200 1.8 Unit Hz % pF ms A
Table 11-9.
Symbol 1/(tCP32KHz)
Note:
11.7.2
Main Oscillators Characteristics
Table 11-10. Main Oscillator Characteristics
Symbol 1/(tCPMAIN) CL1, CL2 CL Parameter Crystal Oscillator Frequency Internal Load Capacitance (CL1 = CL2) Equivalent Load Capacitance Duty Cycle @3MHz @8MHz @16MHz @20MHz Active mode @3 MHz Active mode @8 MHz Active mode @16 MHz Active mode @20 MHz Standby mode @TBD V 150 150 300 400 1 40 Conditions Min 3 12 6 50 60 14.5 4 1.4 1 Typ Max 16 Unit MHz pF pF %
tST
Startup Time
ms
A
IOSC
Current Consumption
A
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11.7.3 PLL Characteristics
Table 11-11. Phase Lock Loop Characteristics
Symbol FOUT FIN Parameter Output Frequency Input Frequency Active mode FVCO@96MHz Active mode FVCO@128MHz Active mode FVCO@160MHz Standby mode Conditions Min 80 4 320 410 450 5 Typ Max 240 32 Unit MHz MHz A A
IPLL
Current Consumption
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11.8 ADC Characteristics
Conditions 10-bit resolution mode 8-bit resolution mode Return from Idle Mode 600 ADC Clock = 5 MHz ADC Clock = 8 MHz ADC Clock = 5 MHz ADC Clock = 8 MHz 2 1.25 384(1) 533(2) Min Typ Max 5 8 20 Units MHz MHz s ns s s kSPS kSPS
Table 11-12. Channel Conversion Time and ADC Clock
Parameter ADC Clock Frequency ADC Clock Frequency Startup Time Track and Hold Acquisition Time Conversion Time Conversion Time Throughput Rate Throughput Rate Notes:
1. Corresponds to 13 clock cycles at 5 MHz: 3 clock cycles for track and hold acquisition time and 10 clock cycles for conversion. 2. Corresponds to 15 clock cycles at 8 MHz: 5 clock cycles for track and hold acquisition time and 10 clock cycles for conversion.
Table 11-13. External Voltage Reference Input
Parameter ADVREF Input Voltage Range ADVREF Average Current Current Consumption on VDDANA On 13 samples with ADC Clock = 5 MHz Conditions Min 2.6 200 Typ Max VDDANA 250 TBD Units V A mA
Table 11-14. Analog Inputs
Parameter Input Voltage Range Input Leakage Current Input Capacitance Min 0 TBD TBD Typ Max VADVREF A pF Units
Table 11-15. Transfer Characteristics
Parameter Resolution Absolute Accuracy Integral Non-linearity Differential Non-linearity Offset Error Gain Error f=5MHz f=5MHz f=5MHz f=5MHz f=5MHz -0.5 -0.5 0.35 0.3 Conditions Min Typ 10 0.8 0.5 0.5 0.5 0.5 Max Units Bit LSB LSB LSB LSB LSB
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11.9
11.9.1
JTAG/ICE Timings
ICE Interface Signals
Table 11-16. ICE Interface Timing Specification
Symbol ICE0 ICE1 ICE2 ICE3 ICE4 ICE5 ICE6 Note: Parameter TCK Low Half-period TCK High Half-period TCK Period TDI, TMS, Setup before TCK High TDI, TMS, Hold after TCK High TDO Hold Time TCK Low to TDO Valid 1. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF Conditions
(1) (1) (1) (1) (1) (1) (1)
Min
Max
Units ns ns ns ns ns ns ns
Figure 11-2. ICE Interface Signals
ICE2 TCK ICE0 ICE1
TMS/TDI ICE3 ICE4
TDO ICE5 ICE6
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11.9.2 JTAG Interface Signals
Table 11-17. JTAG Interface Timing specification
Symbol JTAG0 JTAG1 JTAG2 JTAG3 JTAG4 JTAG5 JTAG6 JTAG7 JTAG8 JTAG9 JTAG10 Note: Parameter TCK Low Half-period TCK High Half-period TCK Period TDI, TMS Setup before TCK High TDI, TMS Hold after TCK High TDO Hold Time TCK Low to TDO Valid Device Inputs Setup Time Device Inputs Hold Time Device Outputs Hold Time TCK to Device Outputs Valid 1. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF Conditions
(1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1)
Min 6 3 9 1 0 4
Max
Units ns ns ns ns ns ns
6
ns ns ns ns ns
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Figure 11-3. JTAG Interface Signals
JTAG2 TCK JTAG JTAG1
0
TMS/TDI JTAG3 JTAG4
TDO JTAG5 JTAG6 Device Inputs JTAG7 JTAG8
Device Outputs JTAG9 JTAG10
11.10 SPI Characteristics
Figure 11-4. SPI Master mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1)
SPCK
SPI0 MISO
SPI1
SPI2 MOSI
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Figure 11-5. SPI Master mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0)
SPCK
SPI3 MISO
SPI4
SPI5 MOSI
Figure 11-6. SPI Slave mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0)
SPCK
SPI6 MISO
SPI7 MOSI
SPI8
Figure 11-7. SPI Slave mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1)
SPCK
SPI9 MISO
SPI10 MOSI
SPI11
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Table 11-18. SPI Timings
Symbol SPI0 SPI1 SPI2 SPI3 SPI4 SPI5 SPI6 SPI7 SPI8 SPI9 SPI10 SPI11 Notes: Parameter MISO Setup time before SPCK rises (master) MISO Hold time after SPCK rises (master) SPCK rising to MOSI Delay (master) MISO Setup time before SPCK falls (master) MISO Hold time after SPCK falls (master) SPCK falling to MOSI Delay (master) SPCK falling to MISO Delay (slave) MOSI Setup time before SPCK rises (slave) MOSI Hold time after SPCK rises (slave) SPCK rising to MISO Delay (slave) MOSI Setup time before SPCK falls (slave) MOSI Hold time after SPCK falls (slave) Conditions 3.3V domain 3.3V domain 3.3V domain 3.3V domain
(1) (1) (1) (1)
Min 22 + (tCPMCK)/2 0
(2)
Max
Units ns ns
7 22 + (tCPMCK)/2 0 7 26.5 0 1.5 27 0 1
(2)
ns ns ns ns ns ns ns ns ns ns
3.3V domain (1) 3.3V domain (1) 3.3V domain 3.3V domain 3.3V domain 3.3V domain 3.3V domain 3.3V domain
(1) (1) (1) (1) (1) (1)
1. 3.3V domain: VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40 pF. 2. tCPMCK: Master Clock period in ns.
11.11 Flash Characteristics
The following table gives the device maximum operating frequency depending on the field FWS of the Flash FSR register. This field defines the number of wait states required to access the Flash Memory.
Table 11-19.
Flash Wait States
FWS 0 1 Read Operations 1 cycle 2 cycles Maximum Operating Frequency (MHz) 33 60
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12. Mechanical Characteristics
12.1
12.1.1
Thermal Considerations
Thermal Data Table 12-1 summarizes the thermal resistance data depending on the package. Table 12-1.
Symbol JA JC JA JC
Thermal Resistance Data
Parameter Junction-to-ambient thermal resistance Junction-to-case thermal resistance Junction-to-ambient thermal resistance Junction-to-case thermal resistance Still Air Condition Still Air Package TQFP64 TQFP64 TQFP48 TQFP48 Typ TBD TBD TBD TBD C/W Unit C/W
12.1.2
Junction Temperature The average chip-junction temperature, TJ, in C can be obtained from the following: 1. 2. T J = T A + ( P D x JA )
T J = T A + ( P D x ( HEATSINK + JC ) )
where: * JA = package thermal resistance, Junction-to-ambient (C/W), provided in Table 12-1 on page 45. * JC = package thermal resistance, Junction-to-case thermal resistance (C/W), provided in Table 12-1 on page 45. * HEAT SINK = cooling device thermal resistance (C/W), provided in the device datasheet. * PD = device power consumption (W) estimated from data provided in the section "Power Consumption" on page 33. * TA = ambient temperature (C). From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature TJ in C.
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12.2 Package Drawings
Figure 12-1. TQFP-64 package drawing
Table 12-2.
TBD
Device and Package Maximum Weight
mg
Table 12-3.
Package Characteristics
TBD
Moisture Sensitivity Level
Table 12-4.
Package Reference
MS-026 E3
JEDEC Drawing Reference JESD97 Classification
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Figure 12-2. TQFP-48 package drawing
Table 12-5.
TBD
Device and Package Maximum Weight
mg
Table 12-6.
Package Characteristics
TBD
Moisture Sensitivity Level
Table 12-7.
Package Reference
MS-026 E3
JEDEC Drawing Reference JESD97 Classification
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Figure 12-3. QFN-64 package drawing
Table 12-8.
TBD
Device and Package Maximum Weight
mg
Table 12-9.
Package Characteristics
TBD
Moisture Sensitivity Level
Table 12-10. Package Reference
JEDEC Drawing Reference JESD97 Classification M0-220 E3
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Figure 12-4. QFN-48 package drawing
Table 12-11. Device and Package Maximum Weight
TBD mg
Table 12-12. Package Characteristics
Moisture Sensitivity Level TBD
Table 12-13. Package Reference
JEDEC Drawing Reference JESD97 Classification M0-220 E3
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12.3
Soldering Profile
Table 12-14 gives the recommended soldering profile from J-STD-20. Table 12-14. Soldering Profile
Profile Feature Average Ramp-up Rate (217C to Peak) Preheat Temperature 175C 25C Temperature Maintained Above 217C Time within 5C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25C to Peak Temperature Note: Green Package TBD TBD TBD TBD TBD TBD TBD
It is recommended to apply a soldering temperature higher than 250C.
A maximum of three reflow passes is allowed per component.
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13. Ordering Information
Temperature Operating Range Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C)
Device AT32UC3B0256 AT32UC3B0128 AT32UC3B064 AT32UC3B1256 AT32UC3B1128 AT32UC3B164
Ordering Code AT32UC3B0256-A2UT AT32UC3B0256-Z2UT AT32UC3B0128-A2UT AT32UC3B0128-Z2UT AT32UC3B064-A2UT AT32UC3B064-Z2UT AT32UC3B1256-AUT AT32UC3B1256-Z1UT AT32UC3B1128-AUT AT32UC3B1128-Z1UT AT32UC3B164-AUT AT32UC3B164-Z1UT
Package TQFP 64 QFN 64 TQFP 64 QFN 64 TQFP 64 QFN 64 TQFP 48 QFN 48 TQFP 48 QFN 48 TQFP 48 QFN 48
Conditioning Tray Tray Tray Tray Tray Tray Tray Tray Tray Tray Tray Tray
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14. Errata
All parts labelled with -ES (for engineering samples) are revision B parts. All part not labelled with -ES are revision E parts.
14.1
Rev. E
This version will be sampled in January 2008.
14.1.1
PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and read the status before channel interrupt is enabled.
14.1.2
SPI 1. SPI Slave / PDCA transfer: no TX UNDERRUN flag There is no TX UNDERRUN flag available, therefore in SPI slave mode, there is no way to be informed of a character lost in transmission. Fix/Workaround For PDCA transfer: none. 2. SPI Bad serial clock generation on 2nd chip select when SCBR=1, CPOL=1 and CNCPHA=0 When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and CPOL=1 and CPHA=0, then an additional pulse will be generated on SCK. Fix/Workaround When multiple CS are in use, if one of the baudrate equals to 1, the other must also equal 1 if CPOL=1 and CPHA=0. 3. SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first transfer In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or during the first transfer. Fix/Workaround 1. Set slave mode, set required CPOL/CPHA. 2. Enable SPI. 3. Set the polarity CPOL of the line in the opposite value of the required one. 4. Set the polarity CPOL to the required one. 5. Read the RXHOLDING register. Transfers can now befin and RXREADY will now behave as expected.
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14.2
14.2.1
Rev. B
Processor and Architecture 1. Local Busto fast GPIO not available on silicon Rev B Local bus is only available for silicon RevE and later. Fix/Workaround Do not use if silicon revison older than E. 2. Memory Protection Unit (MPU) is non functional. Fix/Workaround Do not use the MPU. 3. Bus error should be masked in Debug mode If a bus error occurs during debug mode, the processor will not respond to debug commands through the DINST register. Fix/Workaround A reset of the device will make the CPU respond to debug commands again. 4. Read Modify Write (RMW) instructions on data outside the internal RAM does not work. Read Modify Write (RMW) instructions on data outside the internal RAM does not work. Fix/Workaround Do not perform RMW instructions on data outside the internal RAM. 5. Need two NOPs instruction after instructions masking interrupts The instructions following in the pipeline the instruction masking the interrupt through SR may behave abnormally. Fix/Workaround Place two NOPs instructions after each SSRF or MTSR instruction setting IxM or GM in SR 6. Clock connection table on Rev B Here is the table of Rev B Figure 14-1. Timer/Counter clock connections on RevB
Source Internal Name TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 External XC0 XC1 XC2 Connection Slow Clock (Internal RC oscillator) PBA Clock / 4 PBA Clock / 8 PBA Clock / 16 PBA Clock / 32
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14.2.2
PWM
1. PWM counter restarts at 0x0001 The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first PWM period has one more clock cycle. Fix/Workaround - The first period is 0x0000, 0x0001, ..., period - Consecutive periods are 0x0001, 0x0002, ..., period 2. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 3. PWM update period to a 0 value does not work It is impossible to update a period equal to 0 by the using the PWM update register (PWM_CUPD). Fix/Workaround Do not update the PWM_CUPD register with a value equal to 0. 4. PWM channel status may be wrong if disabled before a period has elapsed Before a PWM period has elapsed, the read channel status may be wrong. The CHIDx-bit for a PWM channel in the PWM Enable Register will read '1' for one full PWM period even if the channel was disabled before the period elapsed. It will then read '0' as expected. Fix/Workaround Reading the PWM channel status of a disabled channel is only correct after a PWM period has elapsed.
14.2.3
SPI 1. SPI FDIV option does not work Selecting clock signal using FDIV = 1 does not work as specified. Fix/Workaround Do not set FDIV = 1. 2. SPI FDIV option does not work Selecting clock signal using FDIV = 1 does not work as specified. Fix/Workaround Do not set FDIV = 1.
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3. SPI Slave / PDCA transfer: no TX UNDERRUN flag There is no TX UNDERRUN flag available, therefore in SPI slave mode, there is no way to be informed of a character lost in transmission. Fix/Workaround For PDCA transfer: none. 4. SPI Bad serial clock generation on 2nd chip select when SCBR=1, CPOL=1 and CNCPHA=0 When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and CPOL=1 and CPHA=0, then an additional pulse will be generated on SCK. Fix/Workaround When multiple CS are in use, if one of the baudrate equals to 1, the other must also equal 1 if CPOL=1 and CPHA=0. 5. SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first transfer In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or during the first transfer. Fix/Workaround 1. Set slave mode, set required CPOL/CPHA. 2. Enable SPI. 3. Set the polarity CPOL of the line in the opposite value of the required one. 4. Set the polarity CPOL to the required one. 5. Read the RXHOLDING register. Transfers can now befin and RXREADY will now behave as expected.
14.2.4
Power Manager 1. PLL Lock control does not work PLL lock Control does not work. Fix/Workaround In PLL Control register, the bit 7 should be set in order to prevent unexpected behaviour. 2. Wrong reset causes when BOD is activated Setting the BOD enable fuse will cause the Reset Cause Register to list BOD reset as the reset source even though the part was reset by another source. Fix/Workaround Do not set the BOD enable fuse, but activate the BOD as soon as your program starts.
14.2.5
SSC 1. SSC does not trigger RF when data is low The SSC cannot transmit or receive data when CKS = CKDIV and CKO = none, in TCMR or RCMR respectively.
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Fix/Workaround Set CKO to a value that is not "none" and bypass the output of the TK/RK pin with the GPIO. 14.2.6 USB 1. USB No end of host reset signaled upon disconnection In host mode, in case of an unexpected device disconnection whereas a usb reset is being sent by the usb controller, the UHCON.RESET bit may not been cleared by the hardware at the end of the reset. Fix/Workaround A software workaround consists in testing (by polling or interrupt) the disconnection (UHINT.DDISCI == 1) while waiting for the end of reset (UHCON.RESET == 0) to avoid being stuck. 2. USBFSM and UHADDR1/2/3 registers are not available. Do not use USBFSM register. Fix/Workaround Do not use USBFSM register and use HCON[6:0] field instead for all the pipes.
14.2.7
Cycle counter 1. CPU Cycle Counter does not reset the COUNT system register on COMPARE match. The device revision B does not reset the COUNT system register on COMPARE match. In this revision, the COUNT register is clocked by the CPU clock, so when the CPU clock stops, so does incrementing of COUNT. Fix/Workaround None.
14.2.8
ADC 1. ADC possible miss on DRDY when disabling a channel The ADC does not work properly when more than one channel is enabled. Fix/Workaround Do not use the ADC with more than one channel enabled at a time. 2. ADC OVRE flag sometimes not reset on Status Register read The OVRE flag does not clear properly if read simultaneously to an end of conversion. Fix/Workaround None.
14.2.9
USART 1. USART Manchester Encoder Not Working Manchester encoding/decoding is not working. Fix/Workaround
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Do not use manchester encoding. 2. USART RXBREAK problem when no timeguard In asynchronous mode the RXBREAK flag is not correctly handled when the timeguard is 0 and the break character is located just after the stop bit. Fix/Workaround If the NBSTOP is 1, timeguard should be different from 0. 3. USART Handshaking: 2 characters sent / CTS rises when TX If CTS switches from 0 to 1 during the TX of a character, if the Holding register is not empty, the TXHOLDING is also transmitted. Fix/Workaround None. 4. USART PDC and TIMEGUARD not supported in MANCHESTER Manchester encoding/decoding is not working. Fix/Workaround Do not use manchester encoding. 5. USART SPI mode is non functional on this revision Fix/Workaround Do not use the USART SPI mode.
14.2.10
HMATRIX 1. HMatrix fixed priority arbitration does not work Fixed priority arbitration does not work. Fix/Workaround Use Round-Robin arbitration instead.
14.2.11
Clock caracteristic 1. PBA max frequency The Peripheral bus A (PBA) max frequency is 30MHz instead of 60MHz. Fix/Workaround Do not set the PBA maximum frequency higher than 30MHz.
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15. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision.
15.1
Rev. E - 12/07
1.
Updated "Memory protection" on page 18.
15.2
Rev. D - 11/07
1. 2.
Updated "The AVR32UC CPU" on page 16.
Updated "Electrical Characteristics" on page 30.
15.3
Rev. C - 10/07
1. 2. 3. 4. 5. 6. 7. 8. 9. 10.
Updated "Features" on page 1. Updated block diagram with local bus Figure 3-1 on page 4. Add schematic for HMatrix master/slave connection Figure 9-1 on page 29. Updated "Peripherals" on page 32 with local bus. Added SPI feature "Universial Synchronous/Asynchronous Receiver/Transmitter (USART)" on page 298. Updated "USB On-The-Go Interface (USBB)" on page 367. Updated ADC trigger selection in "Analog-to-Digital Converter (ADC)" on page 568. Updated "JTAG and Boundary Scan" on page 594 with programming procedure. Add description for silicon revision D page 52. Add ABDAC Chapter
15.4
Rev. B - 07/07
1. 2.
Updated registered trademarks
Updated address page.
15.5
Rev. A - 05/07
1.
Initial revision.
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Table of Contents
1 2 3 Description ............................................................................................... 2 Configuration Summary .......................................................................... 3 Blockdiagram ........................................................................................... 4
3.1Processor and architecture ........................................................................................5
4 5 6
Package and Pinout ................................................................................. 6 Signals Description .................................................................................. 8 Power Considerations ........................................................................... 12
6.1Power Supplies ........................................................................................................12 6.2Voltage Regulator ....................................................................................................13 6.3Analog-to-Digital Converter (A.D.C) reference. .......................................................14
7
I/O Line Considerations ......................................................................... 15
7.1JTAG pins ................................................................................................................15 7.2RESET_N pin ..........................................................................................................15 7.3TWI pins ..................................................................................................................15 7.4GPIO pins ................................................................................................................15 7.5High drive pins .........................................................................................................15
8
Memories ................................................................................................ 16
8.1Embedded Memories ..............................................................................................16 8.2Physical Memory Map .............................................................................................16 8.3Bus Matrix Connections ...........................................................................................17
9
Peripherals .............................................................................................. 19
9.1Peripheral Address Map ..........................................................................................19 9.2CPU Local Bus Mapping .........................................................................................20 9.3Interrupt Request Signal Map ..................................................................................20 9.4Clock Connections ...................................................................................................22 9.5Nexus OCD AUX port connections ..........................................................................23 9.6DMA handshake signals ..........................................................................................23 9.7High Drive Current GPIO .........................................................................................24 9.8Peripheral Multiplexing on I/O lines .........................................................................24 9.9Oscillator Pinout ......................................................................................................25 9.10Peripheral overview ...............................................................................................26
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10 Boot Sequence ....................................................................................... 29
10.1Starting of clocks ...................................................................................................29 10.2Fetching of initial instructions ................................................................................29
11 Electrical Characteristics ...................................................................... 30
11.1Absolute Maximum Ratings* .................................................................................30 11.2DC Characteristics .................................................................................................31 11.3Regulator characteristics .......................................................................................32 11.4Analog characteristics ...........................................................................................32 11.5Power Consumption ..............................................................................................33 11.6Clock Characteristics .............................................................................................35 11.7Crystal Oscillator Characteristis ............................................................................37 11.8ADC Characteristics ..............................................................................................39 11.9JTAG/ICE Timings .................................................................................................40 11.10SPI Characteristics ..............................................................................................42 11.11Flash Characteristics ...........................................................................................44
12 Mechanical Characteristics ................................................................... 45
12.1Thermal Considerations ........................................................................................45 12.2Package Drawings .................................................................................................46 12.3Soldering Profile ....................................................................................................50
13 Ordering Information ............................................................................. 51 14 Errata ....................................................................................................... 52
14.1Rev. E ....................................................................................................................52 14.2Rev. B ....................................................................................................................53
15 Datasheet Revision History ................................................................... 58
15.1Rev. E - 12/07 .......................................................................................................58 15.2Rev. D - 11/07 .......................................................................................................58 15.3Rev. C - 10/07 .......................................................................................................58 15.4Rev. B - 07/07 .......................................................................................................58 15.5Rev. A - 05/07 .......................................................................................................58
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Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
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32059ES-AVR32-12/07

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